Search - ip core

[VHDL-FPGA-Verilog] basicforVHDLIPcoretest

Description: 基于VHDL语言的IP核验证 -VHDL-based IP core verification language
Platform: | Size: 8192 | Author: 张波 | Hits:

[Streaming Mpeg4] rs_enc

Description: 使用IP Core实现了3GPP/UMTS所规定的Turbo码编码，可以在Virtex全系列和Spartan-3E等芯片上使用，最多支持１６路信号，能提供3GPP所要求的1/3码率输出和可选的1/5码率输出-Use IP Core achieved 3GPP/UMTS provided for Turbo-Coded, you can Virtex series and Spartan-3E chip such as the use, supports up to 16-way signal, 3GPP can provide the required 1/3 bit-rate output and optional 1/5 Rate Output
Platform: | Size: 1024 | Author: 刘横 | Hits:

[Other] EHERNETIPcore

Description: 该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
Platform: | Size: 69632 | Author: season | Hits:

[VHDL-FPGA-Verilog] DUC

Description: 数字上变频DUC是与数字下变频ddc相对应的工作.目前实现方式主要有:专用芯片,通用DSP和FPGA实现三种.本程序即给出了XILINX公司的Digital Up Converter核心程序(IP CORE)以及响应的使用说明,对于从事雷达,无线通信的工程人员和研究者有很大用处.-DUC is a digital up-conversion and digital down conversion that corresponds to the work of ddc. Realize the current approach are: ASIC, DSP and FPGA generic realize three. This procedure is given that the company XILINX core Digital Up Converter program (IP CORE) and to respond to instructions, for radar, wireless communications, engineers and researchers have great usefulness.
Platform: | Size: 305152 | Author: 周严 | Hits:

[ActiveX/DCOM/ATL] CORDIC_ip

Description: cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v r : Cordic Mode. r = Rotation, v = Vectoring 32 : Precision of the individual vector components. 16 : Precision of the angle. 12 : Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: | Size: 457728 | Author: abcoabco | Hits:

[Graph program] VGAipcore

Description: vga ip core nios sopc
Platform: | Size: 76800 | Author: yec | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:

[Software Engineering] ps2_ipcore_design

Description: 电子测量技术 ELECTR0NIC MEASI瓜EMENT TECHN0L0GY 第29卷第3期 2006年6月 PS／2设备接口IP核设计王豪黄启俊常胜 (武汉大学物理学院微电子与固体电子学实验室武汉430072) 摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的设计思想，并在FPGA上进行验证。结果表明此核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module
Platform: | Size: 126976 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] AVR

Description: AVR IP CORE 可以直接用于工程的开发和已经通过编译和仿真-AVR IP CORE can be directly used for project development and has passed the compiler and simulation
Platform: | Size: 67584 | Author: 毋杰 | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: RISC CPU IP CORE 可以用于直接的工程开发应用有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
Platform: | Size: 574464 | Author: 毋杰 | Hits:

[Other] mdct.tar

Description: 图像编码如H263 264 AVS等编码都要用DCT变换，DCT变换IP核很有用-Image coding, such as H263 264 AVS must be used, such as DCT transform coding, DCT transform IP core very useful
Platform: | Size: 1770496 | Author: | Hits:

[VHDL-FPGA-Verilog] CF_card_base_on_NiosII

Description: 基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.
Platform: | Size: 1398784 | Author: 沈阳 | Hits:

[VHDL-FPGA-Verilog] uart16550.tar

Description: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
Platform: | Size: 246784 | Author: 姓名 | Hits:

[CA auth] sha1_v01

Description: SHA-1加密算法的IP核，内涵文档，仿真测试文件-SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file
Platform: | Size: 6144 | Author: 徐 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] 8051core

Description: 8051 VHDL IP Core，有兴趣的可以-8051 VHDL IP Core, who are interested can
Platform: | Size: 25600 | Author: lllixplg | Hits:

[VHDL-FPGA-Verilog] IPOFPIC

Description: pic单片机的源代码,基于此IP核可以自己修改单片机的外围设备,并在此基础上开发自己的单片机.-SCM pic source code, based on this IP core can modify MCU peripherals, and on this basis to develop their own single-chip microcomputer.
Platform: | Size: 39936 | Author: luzhao | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Platform: | Size: 1146880 | Author: 蔡飞 | Hits:

[VHDL-FPGA-Verilog] uartvhdl

Description: VHDL语言实现的UART IP核，比较实用-VHDL language to achieve the UART IP core, more practical
Platform: | Size: 412672 | Author: 蔡飞 | Hits:

[Other] I2C

Description: 详细描述了I2C的技术规范版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed description of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
Platform: | Size: 283648 | Author: zyq | Hits:

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